JPEG compression IP core (Verilog)
JPEG compression IP core (Verilog)
Verilog-HDL JPEG compression IP core Compression method: JPEG Base Line method Input format: RGB 8:8:8 Output format: YUV 4:2:0 4:2:2 4:4:4 Huffman coding: Standard settings (Annex K) used Can also be set in registers Quantization table: Standard settings (Annex K) used Can also be set in registers
- Company：メティエ
- Price：Other
